A high resolution continuous time delta-sigma modulator serves as a power efficient candidate with a signal bandwidth ranging from audio band to several megahertz. However, the higher frequency input signal of the continuous time delta-sigma modulator may cause difficult excess loop delay compensation. To solve the excess loop delay compensation problem caused by the high frequency input signal, an additional circuit such as a digital to analog converter (DAC) is arranged to process a feedback signal from an output of the quantizer to an output of the pre-stage loop filter, and therefore there are more than one DACs configured in the excess loop of the continuous time delta-sigma modulator. This additional circuit such as DAC increases the power consumption and provides a large parasitic capacitance to the loop filter.